The purpose of this set of "u-boot complete analysis" course is to take you to appreciate all the software and hardware knowledge involved in embedded development step by step through the whole process analysis of an excellent bootloader software, and unlike those abstract and difficult theoretical courses in universities, we can modify and run the code at any time during the specific analysis of u-boot to test our understanding of knowledge. As long as you go all the way down this process, when your own debugging and writing u-boot is fully running on the development board, you are basically at the intermediate level or above of embedding. Since the foundation of software and hardware has been laid, when you continue to learn the kernel and driver development of software such as Linux and Android, you will no longer feel like you don't understand or difficult to get started. The first and second seasons of this course are the basis of the whole course, and basically after learning the first and second seasons, you can write a bootloader by yourself.
Lecturer introduction
Tegyin Embedded circuitry
bootloader
Expert in the underlying field of operating systems
In the process of embedded teaching, I deeply feel the lack of embedded developers in the current undergraduate professional teaching: because the electronics major has not systematically studied computer professional courses such as "operating system" and "compilation principles", it is difficult to understand a set of huge software structures such as Linux and its compilation and development system and its abstract working mechanism in the later stage. Similarly, computer majors can only stay at the level of pure software development due to lack of comprehensive knowledge of electronic circuit technology and relatively insufficient experience in dealing with hardware.
Only when a developer has all the underlying concrete hardware knowledge and the upper abstract software knowledge can he become an excellent embedded system development engineer. Therefore, in the process of teaching and practice, he pays great attention to the interactive relationship between hardware and software, so that students know what it is and why.
Stage 1 - Prologue
u-boot version selection
Phase 2 - start.s analysis
The anomaly vector of u-boot and the principle of the boot mechanism of V210
Use the objdump disassembly to see u-boot's header code and exception vector handling
ENTRY and other macros, and the setting of CPSR registers
CP15 coprocessor base, VBAR anomaly vector base address mapping
cpu_init_cp15 Subprocess Analysis: Cache operations
cpu_init_cp15 Subprocess Analysis (continued): Branch prediction, MMU operation
cpu_initcrit sub-process analysis, experiment 1: Modify the u-boot source code to display the running status with LED lights
Experiment 1 (continued): Circuit analysis of GPIO input and output
Experiment 1 (continued): The principle of making a U-boot flashing image, MKV210 source code analysis
Experiment 1 (continued): Use the hexdump tool to analyze the hex-decimal code of the image
Overview of the compilation, linking, assembly process
Experiment 2: Write your own boot program: myboot
Experiment 2 (continued): The linking principle of two or more files
Experiment 2 (continued): Disassemble and analyze your own myboot
Experiment 2 (continued): Use Makefile to automatically compile myboot
Experiment 2 (continued): Improve our Makefile
Experiment 2 (continued): Automation variables in Makefile
Phase 3 - lowlevel_init.s analysis
Chip model judgment, reset method judgment
IO hold, reset mode judgment, interrupt initialization
UART initialization and asynchronous communication principles
UART analysis 1
UART analysis 2
UART analysis 3
UART analysis 4
Experiment 3: Use UART to display data in a specified memory
Fundamentals of DDR memory 1
Fundamentals of DDR memory 2
Fundamentals of DDR memory 3
DDR memory hardware connection on V210 open board1
DDR memory hardware connection on V210 open board2
Internal structure of DDR2-Device1
Internal structure of DDR2-Device2
DDR2-operated finite state machine
DDR2 MRS and EMRS registers
DDR2 read and write timings
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Posted on 11/6/2014 5:16:49 PM
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Posted on 11/17/2014 8:18:50 PM
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